Communication bottleneck between memory and logic modules is one of the most serious problems in recent deep submicron very-large-scale integration (VLSI) systems. The programmable computing array is more complex to build and has lower storage density than a normal memory array because of the overhead involved in the storage and logic.
A floating gate MOS transistor is generally used as a memory cell device of flash EEPROMs, which can be back-gated. One example of a back-gated MOSFET transistor is provided in U.S. Pat. No. 7,089,515 entitled, “Threshold Voltage Roll-Off Compensation using Back-Gated MOSFET Devices for System High-Performance and Low Standby Power”, issued Aug. 8, 2006. However, the back-gated transistors in the above referenced patent are directed toward compensating the threshold voltage roll-off.
An example of programmable logic arrays using floating gates is provided in commonly assigned U.S. Pat. No. 6,124,729 entitled, “Field Programmable Logic Arrays with Vertical Transistors”, issued Sep. 26, 2000. The cells therein have a semiconductor pillar providing a shared source and drain region for two separate transistors each having individual floating gates and control lines. Whole arrays of such structures are field programmed together, versus programming on an individual cell basis, in order to function as a particular type of logic plane. In this previous approach, however, the number of connects between planes due to the absence of programmability of each cell independently and need to connect various entire planes in a certain way to achieve a desired logic state may add to the complexity and area consumed by such a layout.